(b) Retention characteristics of the twin poly-Si TFT EEPROM at 8

(b) Retention characteristics of the twin poly-Si TFT EEPROM at 85°C by FN and BBHE. Figure 5 displays a TCAD simulation of FN and BBHE operations. The result indicates that the FN operation produces a high average electric field in the tunneling oxide from the source to the drain, programmed by the tunneling effect. FN operation indicates the average wearing of electric field on the tunneling oxide. BBHE operation produces a sudden electric field peak at the source side, programmed

using hot electrons with high energy, causing considerable local damage to the tunneling oxide. This result of consistent P/E that is caused by FN operation reveals better endurance and retention than the BBHE operation for floating-gate devices. Figure 5 TCAD simulation. (a) FN programming. V FG = V CG × α G = 14.9 V. (b) BBHE programming. V FG = VCG × α G = 5.95 V. Both use the same voltage drop. (c) Electric Antiinfection Compound Library purchase field comparison of FN and BBHE programming. Conclusions This work developed a novel Ω-gate NW-based twin poly-Si TFT

EEPROM. Experimental results demonstrated that the Ω-gate NW-based structure had a large memory window and high P/E efficiency because of its multi-gate structure and even oxide electrical field at the NW corners. After 104 P/E cycles, ΔV th = 3.5 V (72.2%). The proposed twin-TFT EEPROM with a fully overlapped control gate exhibited good data endurance and maintained a wide threshold voltage window even after 104 P/E cycles. BVD-523 This Ω-gate NW-based twin

poly-Si TFT EEPROM can be easily incorporated into an AMLCD array press and SOI CMOS technology without any additional processing. Acknowledgements The authors would like to acknowledge the National Science Council of Taiwan for supporting this research under contract no. NSC 101-2221-E-007-088-MY2. The National Nano Device Laboratories is greatly appreciated for its technical support. References 1. Su CJ, Tsai TI, Lin HC, Huang TS, Chao TY: Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al 2 O 3 stack structure using an implant-free technique. Nanoscale Res Lett 2012, 7:339.CrossRef Carbohydrate 2. Su CJ, Su TK, Tsai TI, Lin HC, Huang TY: A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires. Nanoscale Res Lett 2012, 7:162.CrossRef 3. Park KT, Choi J, Sel J, Kim V, Kang C, Shin Y, Roh U, Park J, Lee JS, Sim J, Jeon S, Lee C, Kim K: A 64-cell NAND flash memory with asymmetric S/D structure for sub-40nm technology and beyond. VLSI Tech Dig 2006, 2006:19. 4. Young ND, Harkin G, Bunn RM, MaCulloch DJ, French ID: The fabrication and characterization of EEPROM arrays on glass using a low-temperature poly-Si TFT process. IEEE Trans Electron Device 1930, 1996:43. 5. Hung MF, Wu YC, Tsai TM, Chen JH, Jhan YR: Enhancement of two-bit performance of dual-pi-gate charge trapping layer flash memory. Applied Physics Express 2012, 5:121801.CrossRef 6.

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